1. 42b063a sim: handle the case when there're not enough HW thread contexts by Tuan Ta · 2 years ago
  2. 2eb57c7 riscv: fixed syscall return value by Tuan Ta · 2 years ago
  3. e437086 cpu: fix how branching is handled when a thread is suspended in MinorCPU by Tuan Ta · 2 years ago
  4. 6a6668b cpu: stop scheduling suspended threads in all stages of MinorCPU by Tuan Ta · 2 years ago
  5. e74921e riscv: ignore nanosleep syscall by Tuan Ta · 2 years ago
  6. bae0edb sim,cpu: make exit_group halt all threads in a group by Tuan Ta · 2 years ago
  7. 72d1d29 arch-riscv: initialize RISC-V's thread pointer register in clone syscall by Tuan Ta · 2 years ago
  8. cf45f22 sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops by Tuan Ta · 2 years ago
  9. e541567 cpu: fixed how O3 CPU executes an exit system call by Tuan Ta · 2 years ago
  10. aefae9d arch-arm: Fix Virtual interrupts in AArch64 by Giacomo Travaglini · 1 year, 2 months ago
  11. 5508866 arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 by Giacomo Travaglini · 1 year, 2 months ago
  12. b7ce897 arch-arm: Allow ArmPPI usage for PMU by Giacomo Travaglini · 1 year, 2 months ago
  13. c2b6aac arch-arm: Fix initialization of PMU counters by Ruben Ayrapetyan · 1 year, 2 months ago
  14. 34b73de configs, arch-arm: Using AddrRange for Realview mem_regions by Giacomo Travaglini · 1 year, 2 months ago
  15. 53eadea configs: Unifiy interpretation of Realview mem_regions by Giacomo Travaglini · 1 year, 2 months ago
  16. 9c5373c arch-riscv: Enable support for riscv 32-bit in SE mode. by Austin Harris · 1 year, 3 months ago
  17. ea487f9 riscv: remove NonSpeculative flag from fence inst by Tuan Ta · 2 years ago
  18. 02dafc5 cpu: fix how a thread starts up in MinorCPU by Tuan Ta · 2 years ago
  19. 8efcc0f arch-riscv: Initialize interrupt mask by Tuan Ta · 1 year, 2 months ago
  20. ff5ad43 scons: fix unused auto-generated blob variable in clang by Ciro Santilli · 1 year, 2 months ago
  21. 9309797 sim: added missed macro definition on MacOS by Andrea Mondelli · 1 year, 2 months ago
  22. 1989ce9 misc: added missing override specifier by Andrea Mondelli · 1 year, 2 months ago
  23. 02d2d7b cpu: Made the Loop Predictor a SimObject by Javier Bueno · 1 year, 2 months ago
  24. 4ba8923 cpu: Made TAGE a SimObject that can be used by other predictors by Jairo Balart · 1 year, 3 months ago
  25. f0e2caf riscv: Get rid of ISA specific register types in Interrupts. by Austin Harris · 1 year, 2 months ago
  26. 2775f55 mem-cache: Updated version of the Signature Path Prefetcher by Javier Bueno · 1 year, 4 months ago
  27. 6684d61 dev, arm: Removed contextId variable by Anouk Van Laer · 1 year, 3 months ago
  28. a119a96 cpu, arch: Replace the CCReg type with RegVal. by Gabe Black · 1 year, 5 months ago
  29. fbdf0b6 python: Remove getCode() type workaround by Andreas Sandberg · 1 year, 2 months ago
  30. 244a984 sim: Prepare C++ side for Python 3 by Andreas Sandberg · 1 year, 2 months ago
  31. 2d1723a tests: Add a helper to run external scripts by Andreas Sandberg · 1 year, 2 months ago
  32. cc59815 tests: Don't override tick rate in Ruby tests by Andreas Sandberg · 1 year, 2 months ago
  33. b6a124d power: Get rid of some ISA specific register types. by Gabe Black · 1 year, 5 months ago
  34. 6ba2888 null: Get rid of some register type definitions. by Gabe Black · 1 year, 5 months ago
  35. cdfb486 mips: Stop using architecture specific register types. by Gabe Black · 1 year, 5 months ago
  36. c8a744f alpha: Stop using architecture specific register types. by Gabe Black · 1 year, 5 months ago
  37. b859a70 x86: Stop using/defining some ISA specific register types. by Gabe Black · 1 year, 5 months ago
  38. ad775e0 riscv: Get rid of some ISA specific register types. by Gabe Black · 1 year, 5 months ago
  39. 5edfb67 arch: cpu: Rename *FloatRegBits* to *FloatReg*. by Gabe Black · 1 year, 5 months ago
  40. 2547416 arch,cpu: Add vector predicate registers by Giacomo Gabrielli · 1 year, 6 months ago
  41. c6f5db8 configs: Enable DTB autogeneration in starter_fs.py by Giacomo Travaglini · 1 year, 2 months ago
  42. 00ef23b arch-arm, configs: Create single instance of DTB autogeneration by Giacomo Travaglini · 1 year, 2 months ago
  43. b2d24ff tests: fix arm regression due to kernel not found by Ciro Santilli · 1 year, 2 months ago
  44. 9048ef0 configs: fs.py remove --generate-dtb and enable it by default by Ciro Santilli · 1 year, 2 months ago
  45. 12eca7a configs, arch-arm: don't search for default DTB and kernel by Ciro Santilli · 1 year, 4 months ago
  46. 9b6f0a9 arch-arm: Remove floatReg operand type by Giacomo Travaglini · 1 year, 3 months ago
  47. 96e72d6 arch-arm: Use VecElem instead of FloatReg for FP instruction by Giacomo Travaglini · 1 year, 4 months ago
  48. d8dd86d arch: Fix VecElem Operand generation in ISA parser by Giacomo Travaglini · 1 year, 4 months ago
  49. 3d15150 cpu, arch, arch-arm: Wire unused VecElem code in the O3 model by Giacomo Travaglini · 1 year, 3 months ago
  50. 204e932 cpu: O3 rename using the flatIndex instead of index by Giacomo Travaglini · 1 year, 3 months ago
  51. 47fd797 arch-arm: Inital vector rename mode depending on A32/A64 by Giacomo Travaglini · 1 year, 3 months ago
  52. b045de7 cpu: Fix VecElemClass bugs in cpu models by Giacomo Travaglini · 1 year, 3 months ago
  53. e7c8154 cpu: Add VecElem entries in MinorCPU Scoreboard by Giacomo Travaglini · 1 year, 3 months ago
  54. 4d44889 arch-arm: Remove unused float operands by Giacomo Travaglini · 1 year, 4 months ago
  55. 3ec5afd arch: Provide traceback when parsing ISA code by Giacomo Travaglini · 1 year, 4 months ago
  56. 48f3829 python: Always throw TypeError on slave-slave connections by Nicholas Lindsay · 1 year, 9 months ago
  57. db190b8 hsail: Remove the MiscReg type. by Gabe Black · 1 year, 5 months ago
  58. d65f3f9 base: arch: Get rid of the now unused FloatRegVal type. by Gabe Black · 1 year, 5 months ago
  59. 34064c4 dev-arm: fix --generate-dtb for ARM by Ciro Santilli · 1 year, 2 months ago
  60. 51becd2 cpu-o3: O3 LSQ Generalisation by Rekai Gonzalez-Alberquilla · 3 years, 2 months ago
  61. 6379beb arch-arm: Implement LoadAcquire/StoreRelease in AArch32 by Giacomo Travaglini · 1 year, 3 months ago
  62. 163065d arch-arm: IsStoreConditional flag set depending on flavor by Giacomo Travaglini · 1 year, 3 months ago
  63. 51aba75 arch-arm: Remove SWP and SWPB instructions by Giacomo Travaglini · 1 year, 3 months ago
  64. e1ef027 systemc: Fix TLM related includes. by Gabe Black · 1 year, 3 months ago
  65. 298e8b8 arm: Replace MiscReg with RegVal in utility.(hh|cc). by Gabe Black · 1 year, 3 months ago
  66. 964e610 mem-ruby: Fix missing TBE allocation and deallocation by Zicong Wang · 1 year, 3 months ago
  67. 1ab1500 sparc: Get rid of some register type definitions. by Gabe Black · 1 year, 6 months ago
  68. 230b892 arch: cpu: Stop passing around misc registers by reference. by Gabe Black · 1 year, 6 months ago
  69. 774770a arm: Get rid of some register type definitions. by Gabe Black · 1 year, 6 months ago
  70. 2b80f58 arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model. by Gabe Black · 1 year, 3 months ago
  71. 0f024be arch-arm: implement the GDB XML target description for ARM by Ciro Santilli · 1 year, 4 months ago
  72. 6064582 ext: import GDB XML target description files for arm by Ciro Santilli · 1 year, 4 months ago
  73. 9712a63 scons: add helpers to access GDB XML description files by Ciro Santilli · 1 year, 4 months ago
  74. f2bda87 scons: allow embedding arbitrary blobs into the gem5 executable by Ciro Santilli · 1 year, 5 months ago
  75. af5a23a base: add support for GDB's XML architecture definition by Ciro Santilli · 1 year, 5 months ago
  76. 12eac0c arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers by Giacomo Travaglini · 1 year, 6 months ago
  77. a0649ee mem: Add tryTiming suppport to CommMonitor by Sascha Bischoff · 1 year, 5 months ago
  78. e9d9575 sim-se add readv and modifies writev by Brandon Potter · 2 years ago
  79. 7936e63 sim-se: add ability to get/set sock metadata by Brandon Potter · 2 years ago
  80. bc74c58 sim-se: add syscalls related to polling by Brandon Potter · 2 years ago
  81. c4e67f6 sim-se: add calls for network transmissions by Brandon Potter · 2 years ago
  82. a2ed7d5 sim-se: add socket-based functionality by Brandon Potter · 2 years ago
  83. 2c9f7eb base: Fix unitialized storage by Daniel R. Carvalho · 1 year, 3 months ago
  84. 5dda7fb tests: Fix tests/main.py so it can be run from anywhere. by Gabe Black · 1 year, 3 months ago
  85. fa0c2bd mem: Allow inserts in the begining of a packet queue by Nikos Nikoleris · 1 year, 4 months ago
  86. ccc50b7 mem: Determine if a packet queue forces ordering at construction by Nikos Nikoleris · 1 year, 4 months ago
  87. 1e9f653 cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum by Nikos Nikoleris · 1 year, 3 months ago
  88. 8c54922 cpu-o3: Make the smtROBPolicy a Param.ScopedEnum by Nikos Nikoleris · 1 year, 3 months ago
  89. 6825ef1 cpu-o3: Make the smtIQPolicy a Param.ScopedEnum by Nikos Nikoleris · 1 year, 3 months ago
  90. 7b4e441 cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum by Nikos Nikoleris · 1 year, 4 months ago
  91. 38339e0 cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum by Nikos Nikoleris · 1 year, 3 months ago
  92. 8ddec57 python: Add support for scoped enums by Nikos Nikoleris · 1 year, 4 months ago
  93. cf0f625 cpu: dev: sim: gpu-compute: Banish some ISA specific register types. by Gabe Black · 1 year, 6 months ago
  94. 0c4515c arch: Make the ISA register types aliases for the global types. by Gabe Black · 1 year, 6 months ago
  95. f4d3328 arm: Make the fp register types 64 bits. by Gabe Black · 1 year, 6 months ago
  96. 6099502 mem-cache: Access Map Pattern Matching Prefetcher by Javier Bueno · 1 year, 4 months ago
  97. 3a3ad05 mem-cache: Signature Path Prefetcher by Javier Bueno · 1 year, 4 months ago
  98. afa039d mem-cache: allow prefetchers to emit page crossing references by Javier Bueno · 1 year, 4 months ago
  99. 38f87da mem-cache: virtual address support for prefetchers by Javier Bueno · 1 year, 5 months ago
  100. cba7585 arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled by Giacomo Travaglini · 1 year, 4 months ago