- 42b063a sim: handle the case when there're not enough HW thread contexts by Tuan Ta · 7 years ago
- 2eb57c7 riscv: fixed syscall return value by Tuan Ta · 7 years ago
- e437086 cpu: fix how branching is handled when a thread is suspended in MinorCPU by Tuan Ta · 7 years ago
- 6a6668b cpu: stop scheduling suspended threads in all stages of MinorCPU by Tuan Ta · 7 years ago
- e74921e riscv: ignore nanosleep syscall by Tuan Ta · 7 years ago
- bae0edb sim,cpu: make exit_group halt all threads in a group by Tuan Ta · 7 years ago
- 72d1d29 arch-riscv: initialize RISC-V's thread pointer register in clone syscall by Tuan Ta · 7 years ago
- cf45f22 sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops by Tuan Ta · 7 years ago
- e541567 cpu: fixed how O3 CPU executes an exit system call by Tuan Ta · 7 years ago
- aefae9d arch-arm: Fix Virtual interrupts in AArch64 by Giacomo Travaglini · 6 years ago
- 5508866 arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 by Giacomo Travaglini · 6 years ago
- b7ce897 arch-arm: Allow ArmPPI usage for PMU by Giacomo Travaglini · 6 years ago
- c2b6aac arch-arm: Fix initialization of PMU counters by Ruben Ayrapetyan · 6 years ago
- 34b73de configs, arch-arm: Using AddrRange for Realview mem_regions by Giacomo Travaglini · 6 years ago
- 53eadea configs: Unifiy interpretation of Realview mem_regions by Giacomo Travaglini · 6 years ago
- 9c5373c arch-riscv: Enable support for riscv 32-bit in SE mode. by Austin Harris · 6 years ago
- ea487f9 riscv: remove NonSpeculative flag from fence inst by Tuan Ta · 7 years ago
- 02dafc5 cpu: fix how a thread starts up in MinorCPU by Tuan Ta · 7 years ago
- 8efcc0f arch-riscv: Initialize interrupt mask by Tuan Ta · 6 years ago
- ff5ad43 scons: fix unused auto-generated blob variable in clang by Ciro Santilli · 6 years ago
- 9309797 sim: added missed macro definition on MacOS by Andrea Mondelli · 6 years ago
- 1989ce9 misc: added missing override specifier by Andrea Mondelli · 6 years ago
- 02d2d7b cpu: Made the Loop Predictor a SimObject by Javier Bueno · 6 years ago
- 4ba8923 cpu: Made TAGE a SimObject that can be used by other predictors by Jairo Balart · 6 years ago
- f0e2caf riscv: Get rid of ISA specific register types in Interrupts. by Austin Harris · 6 years ago
- 2775f55 mem-cache: Updated version of the Signature Path Prefetcher by Javier Bueno · 6 years ago
- 6684d61 dev, arm: Removed contextId variable by Anouk Van Laer · 6 years ago
- a119a96 cpu, arch: Replace the CCReg type with RegVal. by Gabe Black · 6 years ago
- fbdf0b6 python: Remove getCode() type workaround by Andreas Sandberg · 6 years ago
- 244a984 sim: Prepare C++ side for Python 3 by Andreas Sandberg · 6 years ago
- 2d1723a tests: Add a helper to run external scripts by Andreas Sandberg · 6 years ago
- cc59815 tests: Don't override tick rate in Ruby tests by Andreas Sandberg · 6 years ago
- b6a124d power: Get rid of some ISA specific register types. by Gabe Black · 6 years ago
- 6ba2888 null: Get rid of some register type definitions. by Gabe Black · 6 years ago
- cdfb486 mips: Stop using architecture specific register types. by Gabe Black · 6 years ago
- c8a744f alpha: Stop using architecture specific register types. by Gabe Black · 6 years ago
- b859a70 x86: Stop using/defining some ISA specific register types. by Gabe Black · 6 years ago
- ad775e0 riscv: Get rid of some ISA specific register types. by Gabe Black · 6 years ago
- 5edfb67 arch: cpu: Rename *FloatRegBits* to *FloatReg*. by Gabe Black · 6 years ago
- 2547416 arch,cpu: Add vector predicate registers by Giacomo Gabrielli · 6 years ago
- c6f5db8 configs: Enable DTB autogeneration in starter_fs.py by Giacomo Travaglini · 6 years ago
- 00ef23b arch-arm, configs: Create single instance of DTB autogeneration by Giacomo Travaglini · 6 years ago
- b2d24ff tests: fix arm regression due to kernel not found by Ciro Santilli · 6 years ago
- 9048ef0 configs: fs.py remove --generate-dtb and enable it by default by Ciro Santilli · 6 years ago
- 12eca7a configs, arch-arm: don't search for default DTB and kernel by Ciro Santilli · 6 years ago
- 9b6f0a9 arch-arm: Remove floatReg operand type by Giacomo Travaglini · 6 years ago
- 96e72d6 arch-arm: Use VecElem instead of FloatReg for FP instruction by Giacomo Travaglini · 6 years ago
- d8dd86d arch: Fix VecElem Operand generation in ISA parser by Giacomo Travaglini · 6 years ago
- 3d15150 cpu, arch, arch-arm: Wire unused VecElem code in the O3 model by Giacomo Travaglini · 6 years ago
- 204e932 cpu: O3 rename using the flatIndex instead of index by Giacomo Travaglini · 6 years ago
- 47fd797 arch-arm: Inital vector rename mode depending on A32/A64 by Giacomo Travaglini · 6 years ago
- b045de7 cpu: Fix VecElemClass bugs in cpu models by Giacomo Travaglini · 6 years ago
- e7c8154 cpu: Add VecElem entries in MinorCPU Scoreboard by Giacomo Travaglini · 6 years ago
- 4d44889 arch-arm: Remove unused float operands by Giacomo Travaglini · 6 years ago
- 3ec5afd arch: Provide traceback when parsing ISA code by Giacomo Travaglini · 6 years ago
- 48f3829 python: Always throw TypeError on slave-slave connections by Nicholas Lindsay · 7 years ago
- db190b8 hsail: Remove the MiscReg type. by Gabe Black · 6 years ago
- d65f3f9 base: arch: Get rid of the now unused FloatRegVal type. by Gabe Black · 6 years ago
- 34064c4 dev-arm: fix --generate-dtb for ARM by Ciro Santilli · 6 years ago
- 51becd2 cpu-o3: O3 LSQ Generalisation by Rekai Gonzalez-Alberquilla · 8 years ago
- 6379beb arch-arm: Implement LoadAcquire/StoreRelease in AArch32 by Giacomo Travaglini · 6 years ago
- 163065d arch-arm: IsStoreConditional flag set depending on flavor by Giacomo Travaglini · 6 years ago
- 51aba75 arch-arm: Remove SWP and SWPB instructions by Giacomo Travaglini · 6 years ago
- e1ef027 systemc: Fix TLM related includes. by Gabe Black · 6 years ago
- 298e8b8 arm: Replace MiscReg with RegVal in utility.(hh|cc). by Gabe Black · 6 years ago
- 964e610 mem-ruby: Fix missing TBE allocation and deallocation by Zicong Wang · 6 years ago
- 1ab1500 sparc: Get rid of some register type definitions. by Gabe Black · 6 years ago
- 230b892 arch: cpu: Stop passing around misc registers by reference. by Gabe Black · 6 years ago
- 774770a arm: Get rid of some register type definitions. by Gabe Black · 6 years ago
- 2b80f58 arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model. by Gabe Black · 6 years ago
- 0f024be arch-arm: implement the GDB XML target description for ARM by Ciro Santilli · 6 years ago
- 6064582 ext: import GDB XML target description files for arm by Ciro Santilli · 6 years ago
- 9712a63 scons: add helpers to access GDB XML description files by Ciro Santilli · 6 years ago
- f2bda87 scons: allow embedding arbitrary blobs into the gem5 executable by Ciro Santilli · 6 years ago
- af5a23a base: add support for GDB's XML architecture definition by Ciro Santilli · 6 years ago
- 12eac0c arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers by Giacomo Travaglini · 6 years ago
- a0649ee mem: Add tryTiming suppport to CommMonitor by Sascha Bischoff · 6 years ago
- e9d9575 sim-se add readv and modifies writev by Brandon Potter · 7 years ago
- 7936e63 sim-se: add ability to get/set sock metadata by Brandon Potter · 7 years ago
- bc74c58 sim-se: add syscalls related to polling by Brandon Potter · 7 years ago
- c4e67f6 sim-se: add calls for network transmissions by Brandon Potter · 7 years ago
- a2ed7d5 sim-se: add socket-based functionality by Brandon Potter · 7 years ago
- 2c9f7eb base: Fix unitialized storage by Daniel R. Carvalho · 6 years ago
- 5dda7fb tests: Fix tests/main.py so it can be run from anywhere. by Gabe Black · 6 years ago
- fa0c2bd mem: Allow inserts in the begining of a packet queue by Nikos Nikoleris · 6 years ago
- ccc50b7 mem: Determine if a packet queue forces ordering at construction by Nikos Nikoleris · 6 years ago
- 1e9f653 cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum by Nikos Nikoleris · 6 years ago
- 8c54922 cpu-o3: Make the smtROBPolicy a Param.ScopedEnum by Nikos Nikoleris · 6 years ago
- 6825ef1 cpu-o3: Make the smtIQPolicy a Param.ScopedEnum by Nikos Nikoleris · 6 years ago
- 7b4e441 cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum by Nikos Nikoleris · 6 years ago
- 38339e0 cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum by Nikos Nikoleris · 6 years ago
- 8ddec57 python: Add support for scoped enums by Nikos Nikoleris · 6 years ago
- cf0f625 cpu: dev: sim: gpu-compute: Banish some ISA specific register types. by Gabe Black · 6 years ago
- 0c4515c arch: Make the ISA register types aliases for the global types. by Gabe Black · 6 years ago
- f4d3328 arm: Make the fp register types 64 bits. by Gabe Black · 6 years ago
- 6099502 mem-cache: Access Map Pattern Matching Prefetcher by Javier Bueno · 6 years ago
- 3a3ad05 mem-cache: Signature Path Prefetcher by Javier Bueno · 6 years ago
- afa039d mem-cache: allow prefetchers to emit page crossing references by Javier Bueno · 6 years ago
- 38f87da mem-cache: virtual address support for prefetchers by Javier Bueno · 6 years ago
- cba7585 arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled by Giacomo Travaglini · 6 years ago
